Senior RTL Design Engineer

Job Overview

Evaluate architectural trade-offs on features and system limits.

Responsibilities

• Define micro-architecture and implement RTL in Verilog/SystemVerilog.
• Collaborate with verification to ensure full design coverage.
• Provide timing constraints, support synthesis, timing closure, and formality checks.
• Participate in silicon bring-up and validation.

Requirements & Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science.
• 5+ years of RTL implementation ASIC/SoC system integration experience.
• Experience with embedded CPU subsystems and standard bus protocols (e.g. AXI, AHB).
• Scripting skills in Python.
• Experience with stock options, long-term incentives, 401(k) retirement plan, and various insurances.